Job details
| Location: | Hong Kong |
| Salary: | Negotiable |
| Job Type: | Permanent |
| Discipline: | |
| Reference: | 90186_1770090519 |
| Posted: | about 21 hours ago |
Job description
About the client:
Our client is a global leader in the design, development, and delivery of cutting-edge System-on-Chip (SoC) solutions for a wide array of markets, including automotive, data center, networking, and IoT. Currently they're actively seeking a candidate for the Physical Design Engineer.
Key Responsibilities:
- Take ownership of the physical implementation flow from RTL-to-GDSII for high-performance, low-power ASIC/SoC designs.
- Perform synthesis, floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
- Conduct static timing analysis (STA), power analysis, and noise analysis to meet stringent performance, power, and area (PPA) targets.
- Collaborate closely with RTL design, DFT, and analog/mixed-signal teams to ensure design integrity and successful integration.
- Develop and optimize physical design methodologies, scripts, and automation flows to improve efficiency and quality of results (QoR).
- Resolve complex timing, signal integrity, and power grid issues.
- Prepare and release final GDSII tape-out packages, ensuring all physical and electrical sign-off criteria are met.
Qualifications & Experience:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 3+ years of hands-on experience in physical design of ASIC/SoCs in advanced process nodes (7nm, 5nm, or below 20nm etc.).
- Proven experience with the full RTL-to-GDSII flow using industry-standard EDA tools (Synopsys Fusion Compiler, ICC2, Innovus, Primetime, StarRC, etc.).
- Strong understanding of STA concepts, timing constraints, and closure techniques for multi-mode, multi-corner (MMMC) designs.
- Solid experience with power integrity analysis, IR drop, and electromigration (EM) checks.
- Proficiency in scripting languages (Tcl, Perl, Python) for automation and flow development.
- Experience with low-power design techniques (UPF/CPF) and hierarchical design methodologies.
- Excellent problem-solving skills, attention to detail, and a results-oriented mindset.
- Strong verbal and written communication skills and ability to work effectively in a global team environment.
To Apply:
This is a confidential process. To express your interest, please submit your CV and a brief note outlining why your strategic approach and technical expertise are a match for this unique challenge
